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<div class="header">
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<a href="#nested-classes">Data Structures</a> &#124;
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<a href="#typedef-members">Typedefs</a> &#124;
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  <div class="headertitle"><div class="title">Memory CUDA Runtime</div></div>
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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structnvtx_mem_cuda_array_range_desc__v1.html">nvtxMemCudaArrayRangeDesc_v1</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">structure to describe memory in a CUDA array object  <a href="structnvtx_mem_cuda_array_range_desc__v1.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structnvtx_mem_cu_array_range_desc__v1.html">nvtxMemCuArrayRangeDesc_v1</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">structure to describe memory in a CUDA array object  <a href="structnvtx_mem_cu_array_range_desc__v1.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structnvtx_mem_mark_initialized_batch__v1.html">nvtxMemMarkInitializedBatch_v1</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mark memory ranges as initialized.  <a href="structnvtx_mem_mark_initialized_batch__v1.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Macros</h2></td></tr>
<tr class="memitem:gacb334f2ec387c0069fa75fe6bec459bb" id="r_gacb334f2ec387c0069fa75fe6bec459bb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___m_e_m_o_r_y___c_u_d_a_r_t.html#gacb334f2ec387c0069fa75fe6bec459bb">NVTX_MEM_TYPE_CUDA_ARRAY</a>&#160;&#160;&#160;0x11</td></tr>
<tr class="memdesc:gacb334f2ec387c0069fa75fe6bec459bb"><td class="mdescLeft">&#160;</td><td class="mdescRight">The memory is from a CUDA runtime array.  <br /></td></tr>
<tr class="separator:gacb334f2ec387c0069fa75fe6bec459bb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga16e14ba99fe35f86514cde7a791021aa" id="r_ga16e14ba99fe35f86514cde7a791021aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___m_e_m_o_r_y___c_u_d_a_r_t.html#ga16e14ba99fe35f86514cde7a791021aa">NVTX_MEM_TYPE_CU_ARRAY</a>&#160;&#160;&#160;0x12</td></tr>
<tr class="memdesc:ga16e14ba99fe35f86514cde7a791021aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">The memory is from a CUDA device array.  <br /></td></tr>
<tr class="separator:ga16e14ba99fe35f86514cde7a791021aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0ff3290abfdd4de6ab40472dc41f3751" id="r_ga0ff3290abfdd4de6ab40472dc41f3751"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___m_e_m_o_r_y___c_u_d_a_r_t.html#ga0ff3290abfdd4de6ab40472dc41f3751">NVTX_MEM_CUDA_PEER_ALL_DEVICES</a>&#160;&#160;&#160;-1</td></tr>
<tr class="separator:ga0ff3290abfdd4de6ab40472dc41f3751"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Typedefs</h2></td></tr>
<tr class="memitem:gaf6a8330b248342b5b07239fa1d722b35" id="r_gaf6a8330b248342b5b07239fa1d722b35"><td class="memItemLeft" align="right" valign="top">typedef <a class="el" href="structnvtx_mem_cuda_array_range_desc__v1.html">nvtxMemCudaArrayRangeDesc_v1</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___m_e_m_o_r_y___c_u_d_a_r_t.html#gaf6a8330b248342b5b07239fa1d722b35">nvtxMemCudaArrayRangeDesc_t</a></td></tr>
<tr class="separator:gaf6a8330b248342b5b07239fa1d722b35"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga75458e1d4befde4f9b2da3768d6ca968" id="r_ga75458e1d4befde4f9b2da3768d6ca968"><td class="memItemLeft" align="right" valign="top">typedef <a class="el" href="structnvtx_mem_cu_array_range_desc__v1.html">nvtxMemCuArrayRangeDesc_v1</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___m_e_m_o_r_y___c_u_d_a_r_t.html#ga75458e1d4befde4f9b2da3768d6ca968">nvtxMemCuArrayRangeDesc_t</a></td></tr>
<tr class="separator:ga75458e1d4befde4f9b2da3768d6ca968"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7e1c95b4125c9753a007558b0db10b64" id="r_ga7e1c95b4125c9753a007558b0db10b64"><td class="memItemLeft" align="right" valign="top">typedef <a class="el" href="structnvtx_mem_mark_initialized_batch__v1.html">nvtxMemMarkInitializedBatch_v1</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___m_e_m_o_r_y___c_u_d_a_r_t.html#ga7e1c95b4125c9753a007558b0db10b64">nvtxMemMarkInitializedBatch_t</a></td></tr>
<tr class="separator:ga7e1c95b4125c9753a007558b0db10b64"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:gab620d175752a7d8f653b543b123ff39d" id="r_gab620d175752a7d8f653b543b123ff39d"><td class="memItemLeft" align="right" valign="top">NVTX_DECLSPEC <a class="el" href="group___m_e_m_o_r_y.html#ga421ec4c6d96c342008aa3d04906643f0">nvtxMemPermissionsHandle_t</a> NVTX_API&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___m_e_m_o_r_y___c_u_d_a_r_t.html#gab620d175752a7d8f653b543b123ff39d">nvtxMemCudaGetProcessWidePermissions</a> (nvtxDomainHandle_t domain)</td></tr>
<tr class="memdesc:gab620d175752a7d8f653b543b123ff39d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the permission object that represent the CUDA runtime device or cuda driver context.  <br /></td></tr>
<tr class="separator:gab620d175752a7d8f653b543b123ff39d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8590f26d90d3bae446b20f45e2fa1f67" id="r_ga8590f26d90d3bae446b20f45e2fa1f67"><td class="memItemLeft" align="right" valign="top">NVTX_DECLSPEC <a class="el" href="group___m_e_m_o_r_y.html#ga421ec4c6d96c342008aa3d04906643f0">nvtxMemPermissionsHandle_t</a> NVTX_API&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___m_e_m_o_r_y___c_u_d_a_r_t.html#ga8590f26d90d3bae446b20f45e2fa1f67">nvtxMemCudaGetDeviceWidePermissions</a> (nvtxDomainHandle_t domain, int device)</td></tr>
<tr class="memdesc:ga8590f26d90d3bae446b20f45e2fa1f67"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the permission object that represent the CUDA runtime device or cuda driver context.  <br /></td></tr>
<tr class="separator:ga8590f26d90d3bae446b20f45e2fa1f67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab206e393eb36a38670ed44c88f1df217" id="r_gab206e393eb36a38670ed44c88f1df217"><td class="memItemLeft" align="right" valign="top">NVTX_DECLSPEC void NVTX_API&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___m_e_m_o_r_y___c_u_d_a_r_t.html#gab206e393eb36a38670ed44c88f1df217">nvtxMemCudaSetPeerAccess</a> (nvtxDomainHandle_t domain, <a class="el" href="group___m_e_m_o_r_y.html#ga421ec4c6d96c342008aa3d04906643f0">nvtxMemPermissionsHandle_t</a> permissions, int devicePeer, uint32_t flags)</td></tr>
<tr class="memdesc:gab206e393eb36a38670ed44c88f1df217"><td class="mdescLeft">&#160;</td><td class="mdescRight">Change the default behavior for all memory mapped in from a particular device.  <br /></td></tr>
<tr class="separator:gab206e393eb36a38670ed44c88f1df217"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0d8a3745a6812aa75ef3d2279c012259" id="r_ga0d8a3745a6812aa75ef3d2279c012259"><td class="memItemLeft" align="right" valign="top">NVTX_DECLSPEC void NVTX_API&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___m_e_m_o_r_y___c_u_d_a_r_t.html#ga0d8a3745a6812aa75ef3d2279c012259">nvtxMemCudaMarkInitialized</a> (nvtxDomainHandle_t domain, cudaStream_t stream, uint8_t isPerThreadStream, <a class="el" href="structnvtx_mem_mark_initialized_batch__v1.html">nvtxMemMarkInitializedBatch_t</a> const *desc)</td></tr>
<tr class="memdesc:ga0d8a3745a6812aa75ef3d2279c012259"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register a region of memory inside of a heap of linear process virtual memory.  <br /></td></tr>
<tr class="separator:ga0d8a3745a6812aa75ef3d2279c012259"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<p>See page PAGE_MEMORY_CUDART. </p>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="ga0ff3290abfdd4de6ab40472dc41f3751" name="ga0ff3290abfdd4de6ab40472dc41f3751"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga0ff3290abfdd4de6ab40472dc41f3751">&#9670;&#160;</a></span>NVTX_MEM_CUDA_PEER_ALL_DEVICES</h2>

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          <td class="memname">#define NVTX_MEM_CUDA_PEER_ALL_DEVICES&#160;&#160;&#160;-1</td>
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<p class="definition">Definition at line <a class="el" href="nv_tools_ext_mem_cuda_rt_8h_source.html#l00101">101</a> of file <a class="el" href="nv_tools_ext_mem_cuda_rt_8h_source.html">nvToolsExtMemCudaRt.h</a>.</p>

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<a id="ga16e14ba99fe35f86514cde7a791021aa" name="ga16e14ba99fe35f86514cde7a791021aa"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga16e14ba99fe35f86514cde7a791021aa">&#9670;&#160;</a></span>NVTX_MEM_TYPE_CU_ARRAY</h2>

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          <td class="memname">#define NVTX_MEM_TYPE_CU_ARRAY&#160;&#160;&#160;0x12</td>
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<p>The memory is from a CUDA device array. </p>
<p>Relevant functions: cuArrayCreate, cuArray3DCreate Also CUarray from other types such as CUmipmappedArray</p>
<p>NVTX_MEM_HEAP_HANDLE_PROCESS_WIDE is not supported</p>
<p>nvtxMemHeapRegister receives a heapDesc of type cudaArray_t because the description can be retrieved by tools through cudaArrayGetInfo() nvtxMemRegionRegisterEx receives a regionDesc of type nvtxMemCuArrayRangeDesc_t </p>

<p class="definition">Definition at line <a class="el" href="nv_tools_ext_mem_cuda_rt_8h_source.html#l00084">84</a> of file <a class="el" href="nv_tools_ext_mem_cuda_rt_8h_source.html">nvToolsExtMemCudaRt.h</a>.</p>

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<a id="gacb334f2ec387c0069fa75fe6bec459bb" name="gacb334f2ec387c0069fa75fe6bec459bb"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gacb334f2ec387c0069fa75fe6bec459bb">&#9670;&#160;</a></span>NVTX_MEM_TYPE_CUDA_ARRAY</h2>

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          <td class="memname">#define NVTX_MEM_TYPE_CUDA_ARRAY&#160;&#160;&#160;0x11</td>
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<p>The memory is from a CUDA runtime array. </p>
<p>Relevant functions: cudaMallocArray, cudaMalloc3DArray Also cudaArray_t from other types such as cudaMipmappedArray_t</p>
<p>NVTX_MEM_HEAP_HANDLE_PROCESS_WIDE is not supported</p>
<p>nvtxMemHeapRegister receives a heapDesc of type cudaArray_t because the description can be retrieved by tools through cudaArrayGetInfo() nvtxMemRegionRegisterEx receives a regionDesc of type nvtxMemCudaArrayRangeDesc_t </p>

<p class="definition">Definition at line <a class="el" href="nv_tools_ext_mem_cuda_rt_8h_source.html#l00058">58</a> of file <a class="el" href="nv_tools_ext_mem_cuda_rt_8h_source.html">nvToolsExtMemCudaRt.h</a>.</p>

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<h2 class="groupheader">Typedef Documentation</h2>
<a id="ga75458e1d4befde4f9b2da3768d6ca968" name="ga75458e1d4befde4f9b2da3768d6ca968"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga75458e1d4befde4f9b2da3768d6ca968">&#9670;&#160;</a></span>nvtxMemCuArrayRangeDesc_t</h2>

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          <td class="memname">typedef <a class="el" href="structnvtx_mem_cu_array_range_desc__v1.html">nvtxMemCuArrayRangeDesc_v1</a> <a class="el" href="structnvtx_mem_cu_array_range_desc__v1.html">nvtxMemCuArrayRangeDesc_t</a></td>
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<p class="definition">Definition at line <a class="el" href="nv_tools_ext_mem_cuda_rt_8h_source.html#l00097">97</a> of file <a class="el" href="nv_tools_ext_mem_cuda_rt_8h_source.html">nvToolsExtMemCudaRt.h</a>.</p>

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<a id="gaf6a8330b248342b5b07239fa1d722b35" name="gaf6a8330b248342b5b07239fa1d722b35"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf6a8330b248342b5b07239fa1d722b35">&#9670;&#160;</a></span>nvtxMemCudaArrayRangeDesc_t</h2>

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          <td class="memname">typedef <a class="el" href="structnvtx_mem_cuda_array_range_desc__v1.html">nvtxMemCudaArrayRangeDesc_v1</a> <a class="el" href="structnvtx_mem_cuda_array_range_desc__v1.html">nvtxMemCudaArrayRangeDesc_t</a></td>
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<p class="definition">Definition at line <a class="el" href="nv_tools_ext_mem_cuda_rt_8h_source.html#l00071">71</a> of file <a class="el" href="nv_tools_ext_mem_cuda_rt_8h_source.html">nvToolsExtMemCudaRt.h</a>.</p>

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<a id="ga7e1c95b4125c9753a007558b0db10b64" name="ga7e1c95b4125c9753a007558b0db10b64"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7e1c95b4125c9753a007558b0db10b64">&#9670;&#160;</a></span>nvtxMemMarkInitializedBatch_t</h2>

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          <td class="memname">typedef <a class="el" href="structnvtx_mem_mark_initialized_batch__v1.html">nvtxMemMarkInitializedBatch_v1</a> <a class="el" href="structnvtx_mem_mark_initialized_batch__v1.html">nvtxMemMarkInitializedBatch_t</a></td>
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<p class="definition">Definition at line <a class="el" href="nv_tools_ext_mem_cuda_rt_8h_source.html#l00184">184</a> of file <a class="el" href="nv_tools_ext_mem_cuda_rt_8h_source.html">nvToolsExtMemCudaRt.h</a>.</p>

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<h2 class="groupheader">Function Documentation</h2>
<a id="ga8590f26d90d3bae446b20f45e2fa1f67" name="ga8590f26d90d3bae446b20f45e2fa1f67"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8590f26d90d3bae446b20f45e2fa1f67">&#9670;&#160;</a></span>nvtxMemCudaGetDeviceWidePermissions()</h2>

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          <td class="memname">NVTX_DECLSPEC <a class="el" href="group___m_e_m_o_r_y.html#ga421ec4c6d96c342008aa3d04906643f0">nvtxMemPermissionsHandle_t</a> NVTX_API nvtxMemCudaGetDeviceWidePermissions </td>
          <td>(</td>
          <td class="paramtype">nvtxDomainHandle_t&#160;</td>
          <td class="paramname"><em>domain</em>, </td>
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          <td class="paramkey"></td>
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          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>device</em>&#160;</td>
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          <td></td>
          <td>)</td>
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<p>Get the permission object that represent the CUDA runtime device or cuda driver context. </p>
<p>This object will allow developers to adjust permissions applied to work executed on the GPU. It may be inherited or overridden by permissions object bound with NVTX_MEM_PERMISSIONS_BIND_SCOPE_CUDA_STREAM, depending on the binding flags.</p>
<p>Ex. change the peer to peer access permissions between devices in entirety or punch through special holes</p>
<p>By default, all memory is accessible that naturally would be to a CUDA kernel until modified otherwise by nvtxMemCudaSetPeerAccess or changing regions.</p>
<p>This object should also represent the CUDA driver API level context. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gab620d175752a7d8f653b543b123ff39d">&#9670;&#160;</a></span>nvtxMemCudaGetProcessWidePermissions()</h2>

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          <td class="memname">NVTX_DECLSPEC <a class="el" href="group___m_e_m_o_r_y.html#ga421ec4c6d96c342008aa3d04906643f0">nvtxMemPermissionsHandle_t</a> NVTX_API nvtxMemCudaGetProcessWidePermissions </td>
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          <td class="paramtype">nvtxDomainHandle_t&#160;</td>
          <td class="paramname"><em>domain</em></td><td>)</td>
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<p>Get the permission object that represent the CUDA runtime device or cuda driver context. </p>
<p>This object will allow developers to adjust permissions applied to work executed on the GPU. It may be inherited or overridden by permissions object bound with NVTX_MEM_PERMISSIONS_BIND_SCOPE_CUDA_STREAM, depending on the binding flags.</p>
<p>Ex. change the peer to peer access permissions between devices in entirety or punch through special holes</p>
<p>By default, all memory is accessible that naturally would be to a CUDA kernel until modified otherwise by nvtxMemCudaSetPeerAccess or changing regions.</p>
<p>This object should also represent the CUDA driver API level context. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga0d8a3745a6812aa75ef3d2279c012259">&#9670;&#160;</a></span>nvtxMemCudaMarkInitialized()</h2>

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          <td class="memname">NVTX_DECLSPEC void NVTX_API nvtxMemCudaMarkInitialized </td>
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          <td class="paramtype">cudaStream_t&#160;</td>
          <td class="paramname"><em>stream</em>, </td>
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          <td class="paramtype">uint8_t&#160;</td>
          <td class="paramname"><em>isPerThreadStream</em>, </td>
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          <td class="paramtype"><a class="el" href="structnvtx_mem_mark_initialized_batch__v1.html">nvtxMemMarkInitializedBatch_t</a> const *&#160;</td>
          <td class="paramname"><em>desc</em>&#160;</td>
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<p>Register a region of memory inside of a heap of linear process virtual memory. </p>
<p>stream is the CUDA stream where the range was accessed and initialized. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gab206e393eb36a38670ed44c88f1df217">&#9670;&#160;</a></span>nvtxMemCudaSetPeerAccess()</h2>

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          <td class="memname">NVTX_DECLSPEC void NVTX_API nvtxMemCudaSetPeerAccess </td>
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          <td class="paramtype"><a class="el" href="group___m_e_m_o_r_y.html#ga421ec4c6d96c342008aa3d04906643f0">nvtxMemPermissionsHandle_t</a>&#160;</td>
          <td class="paramname"><em>permissions</em>, </td>
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          <td class="paramname"><em>devicePeer</em>, </td>
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<p>Change the default behavior for all memory mapped in from a particular device. </p>
<p>While typically all memory defaults to readable and writable, users may desire to limit access to reduced default permissions such as read-only and a per-device basis.</p>
<p>Regions can used to further override smaller windows of memory.</p>
<p>devicePeer can be NVTX_MEM_CUDA_PEER_ALL_DEVICES </p>

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